Renesas Evaluation Boards User Forum: SCI, H8S, H82134

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SCI, H8S, H82134

Posted by wiloertel on October 17, 2003, 9:47:06
195.180.3.114

I'm using the SCI with TXI interrupt without DTC. When the TDRE bit is set and the TXI is invoked, but there are no more data to send: Do I have to disable the TXI with TIE=0 to prevent further TXI interrupts or not. With other words: Is the TXI level triggered or edge triggerd by the TDRE bit?
I know the SCI error inerrupts are level triggered by their bits (ORER,PER,FER).

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SCI, H8S, H82134 - wiloertel October 17, 2003, 9:47:06
- Re: SCI, H8S, H82134 - Dexter October 27, 2003, 13:12:42
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--Previous Message-- : I'm using the SCI with TXI interrupt : without DTC. When the TDRE bit is : set and the TXI is invoked, but : there are no more data to send: Do I : have to disable the TXI with TIE=0 : to prevent further TXI interrupts or : not. With other words: Is the TXI : level triggered or edge triggerd by : the TDRE bit? : I know the SCI error inerrupts are : level triggered by their bits : (ORER,PER,FER). : :

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