Posted by GA on April 22, 2003, 8:59:48, in reply to "Using interrupts on EVB2623" I would suspect that you are not enabling the TPU in the module stop register. By default this peripheral is disabled and must be enabled BEFORE any of its registers are accessed. You won't see this problem with HDI-M as part of HDI-M's initialisation enables all of the peripherals. The TPU can be enabled by clearing bit 5 in the MSTPCRA register. See the power down modes section of the hardware manual for more details. GA --Previous Message--
194.131.190.3
Yash,
: Hi,
: I am using GNUH8 (h8300-coff-gcc) to
: build an application for EVB2623.
: Following is a simple interrupt
: program which works very well
: thro' HDI but when flashed does
: not work.
: The program simply toogles the LED on
: EVB ( port 1.5 ) when interrupt
: (Channel 3 overflow) is generated.
: I have made sure that program comes
: till while(1); loop using LED'
: (before interrupt is enabled)
: Am I missing something ?
: Could some help to solve the problem
: ?
: -----------------Program Start
: ---------------
: #include "ioh82623.h"
: typedef void (*fp) (void);
: void start (void);
: void timer3_OV_isr(void)
: __attribute__((interrupt_handler));
: __inline__ void set_interrupt_mask
: (unsigned char mask) __attribute__
: ((always_inline));
: extern __inline__ void
: set_interrupt_mask (unsigned char
: mask)
: {
: asm ("mov %0l,
: r0l"::"r"(mask));
: asm ("and.b #01,r0l"
;
: asm ("rotr.b r0l";
: asm ("ldc r0l,ccr";
: }
: const fp HardwareVectors[]
: __attribute__ ((section
: (".vects")) = {
: #ifndef ROMSTART // HDI-M / GDB-Stub
: - Shadow Vector
: 0x5a000000 + start, /* 0 - Reset
: vector */
: #else
: start, /* 0 - Reset vector */
: #endif
: (fp)(0), /* 1 - Manual reset */
: (fp)(0), (fp)(0), (fp)(0), /*
: 2,3,4 - Reserved */
: (fp)(0), /* 5 - Trace */
: (fp)(0), /* 6 - Direct Transitions
: */
: (fp)(0), /* 7 - NMI */
: (fp)(0), (fp)(0), (fp)(0), (fp)(0),
: /* 8,9,10,11 - Trap */
: (fp)(0), (fp)(0), (fp)(0), (fp)(0),
: /* 12,13,14,15 - Reserved */
: (fp)(0), /* 16 - IRQ0 */
: (fp)(0), /* 17 - IRQ1 */
: (fp)(0), /* 18 - IRQ2 */
: (fp)(0), /* 19 - IRQ3 */
: (fp)(0), /* 20 - IRQ4 */
: (fp)(0), /* 21 - IRQ5 */
: (fp)(0), (fp)(0), /* 22,23 -
: Reserved */
: (fp)(0), /* 24 - DTC*/
: (fp)(0), /* 25 - Watchdog timer 0
: */
: (fp)(0), /* 26 - Reserved */
: (fp)(0), /* 27 - PC Break */
: (fp)(0), /* 28 - AD */
: (fp)(0), /* 29 - Watchdog Timer 1
: */
: (fp)(0), (fp)(0), /* 30,31 -
: Reserved */
: /* 32 to 36 TPU Channel 0 */
: (fp)(0), /* 32 - TGI0A */
: (fp)(0), /* 33 - TGI0B */
: (fp)(0), /* 34 - TGI0C */
: (fp)(0), /* 35 - TGI0D */
: (fp)(0), /* 36 - TGI0V */
: (fp)(0), (fp)(0), (fp)(0),/* 37,38,
: 39 - Reserved */
: /* 40 to 43 TPU Channel 1 */
: (fp)(0), /* 40 - TGI1A */
: (fp)(0), /* 41 - TGI1B */
: (fp)(0), /* 42 - TGI1V */
: (fp)(0), /* 43 - TGI1U */
: /* 44 to 47 TPU Channel 2 */
: (fp)(0), /* 44 - TGI2A */
: (fp)(0), /* 45 - TGI2B */
: (fp)(0), /* 46 - TGI2V */
: (fp)(0), /* 47 - TGI2U */
: /* 48 to 52 TPU Channel 3 */
: (fp)(0), /* 48 - TGI3A */
: (fp)(0), /* 49 - TGI3B */
: (fp)(0), /* 50 - TGI3C */
: (fp)(0), /* 51 - TGI3D */
: #ifndef ROMSTART // HDI-M / GDB-Stub
: - Shadow Vector
: 0x5a000000 + timer3_OV_isr, /* 52 -
: TGI3V */
: #else
: timer3_OV_isr, /* 52 - TGI3V */
: #endif
: (fp)(0), (fp)(0), (fp)(0), /*
: 53,54, 55 - Reserved */
: };
:
: void timer3_OV_isr(void)
: {
: unsigned char c;
: /* Timer Status Register 3
: Bit 4 = Overflow clear */
: c = TPU_TSR3;
: P1DR ^= 0x20; /* Toggle LED */
: TPU_TCNT3 = 0x0000;
: TPU_TSR3 = c & 0xEF; /* Clear
: Overflow */
: }
: void timer3_init(void)
: {
: /* Channel 3 TCR - Timer Control
: Regiter
: Bit 7,6,5 - 0 ; TCNT Clearing
: Disabled
: Bit 4,3 - 0 ; Rising edge
: Bit 2,1,0 - 3 , Internal Clock /64
: */
: TPU_TCR3 = 0x3;
: /*
: Timer Mode Register TMDR3
: Bit 7,6 - 3 ; Reserved
: Bit 5 - 0 ; TGRB Operates normally
: Bit 4 - 0 ; TGRA Operates normally
: Bit 3,2,1,0 - 0 ; Normal operation
: */
: TPU_TMDR3 = 0xc0;
: /* Timer interrupt Enable register
: Bit 7 - 0 ; A/D conversion start
: request generation disabled
: Bit 6 = 0 ,5 = 1 ; Reserved
: Bit 4 = 1 ; Interrupt requests
: (TCIV) by TCFV enabled
: Bit 3,2,1,0 = 0 ; D,C,B and A
: disabled.
: */
: TPU_TIER3 = 0x30;
: /* Load Counter value */
: TPU_TCNT3 = 0x0000;
: ITU_TSTR = 0x08; /* Start Channel 3
: */
: set_interrupt_mask(0);
: }
: void hw_initialise (void)
: {
: ABWCR = 0xFC ; /* */
: ASTCR = 0xFF ; /* */
: WCRL = 0xFC ; /* */
: BCRH = 0xD0 ; /* */
: PFCR = 0x0F ; /* */
: PCDDR = 0xFF ; /* */
: }
: int main(void)
: {
: P1DDR |= 0x20; /* set port1/bit 5
: for output */
: timer3_init();
: while(1);
: }
: -----------------Program
: End---------------
: I can send the complete project if
: required.
: Thank you in advance.
: Yash
:
:
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