Renesas Evaluation Boards User Forum: H8S/2633 & DMAC

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H8S/2633 & DMAC

Posted by Dave Bryan on December 17, 2002, 15:19:08
212.134.84.248

If I configure 4 channels of DMAC to be activated by the same interrupt how many CPU cycles are used to select the next lowest priority DMAC channel i.e. are there 2 cycles delays to access re-acquire the bus between successive DMAC transfers ?

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H8S/2633 & DMAC - Dave Bryan December 17, 2002, 15:19:08
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--Previous Message-- : If I configure 4 channels of DMAC to : be activated by the same interrupt : how many CPU cycles are used to : select the next lowest priority DMAC : channel i.e. are there 2 cycles : delays to access re-acquire the bus : between successive DMAC transfers ? :

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