Renesas Evaluation Boards User Forum: Re: sh3 interrupts

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Re: sh3 interrupts

Posted by Knott on July 1, 2002, 12:56:56

At power up the BL bit in the SH3 SR (status register) is set to 1, i.e. block all interupts. Also the bits I3 to I0 are set to 1in the SR, giving an interupt mask level of the highest level. Check how you have these configured in your startup code, these may not have been changed from the power on values.
KT
--Previous Message--
: Can anybody help me with interrupts on
: a sh3 processor? I just can't get
: it to work, it just doesn't jump
: to VBR + 600 adress...
:

Message Thread:

sh3 interrupts - Mathieu May 29, 2002, 11:04:29
- Re: sh3 interrupts - Knott July 1, 2002, 12:56:56
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--Previous Message-- : At power up the BL bit in the SH3 SR : (status register) is set to 1, i.e. : block all interupts. Also the bits : I3 to I0 are set to 1in the SR, : giving an interupt mask level of the : highest level. Check how you have : these configured in your startup : code, these may not have been : changed from the power on values. : : KT : : --Previous Message-- : Can anybody help me with interrupts : on : a sh3 processor? I just can't get : it to work, it just doesn't jump : to VBR + 600 adress... : : :

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